Abstract
In order to obtain high yields during IC manufacturing, particles - added during layer deposition, etching … - have to be removed. In order to meet the stringent requirements set by the ITRS roadmap, this cleaning has to occur with minimal substrate etching. This necessitates the use of physically-assisted particle-removal techniques, e.g. megasonic cleaning. These methods are usually evaluated on blanket wafers. However, many cleaning steps occur on patterned wafers. The goal of this paper is to investigate the particle removal efficiency (PRE) for patterned substrates compared to blanket wafers. A full-wafer contamination and detection protocol was developed to evaluate the removal efficiencies of micron-wide trenches. The student-t test reveals a significantly lower PRE for 1μm wide by 2.2 μm deep trenches versus a blanket wafer for megasonic cleaning. This is relevant for STI cleaning and cleaning of dielectric trenches in damascene patterning.
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