The Reliability of Integrated Injection Logic Circuits for the Bell System

Abstract

The reliability of Integrated Injection Logic (I2L) or Merged Transistor Logic (MTL) circuits fabricated in a standard bipolar technology with Ti-Pt-Au interconnection is reported. The study is based on accelerated stress aging and actual field results. Experiments are described which demonstrate that I2L circuit failure in humid ambients due to Au elelctrolysis will not occur because of low voltage operation. Failure rates less than 10 FITs for an LSI part (.001% failure per 1000 device hours) under normal stress over a 40 year life are predicted for the main population by accelerated bias temperature and bias humidity stress. Well behaved current gain (ßu) under bias temperature step stress indicates that Ou degradation will not be a significant failure mechanism. At this writing, more than 60 million device hours have been accumulated for LSI chips in specific applications with no reported chip failures. This field result firmly supports accelerated stress reliability predictions.