Abstract
The role of Ti-W/Au bumping in reliability and hermeticity testing environments has been studied using both epoxy- and silicon-encapsulated tape automated bonding (TAB) chips, plastic chip carriers and bare TAB chips, with and without bump test openings. Aging was performed in 85°C and 85% relative humidity conditions and measurements were carried out with electrical testing equipment. Covering all the critical openings on the passivation with Ti-W/Au bumps was found to be a very effective way to improve the reliability especially in humid conditions, where the failure mechanism is often based on the joint surfaces at the opening area. Mechanical protection was found to be the only purpose for die-level encapsulation because high reliability was achieved by bumping all test patterns. Furthermore, a method for total chip passivation based on Ti-W/Au bumping was evaluated for the mass bonding processes.
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