Abstract
The reconfigurable-hardware real-time power system simulator (RH-RTS) is a field-programmable gate-array (FPGA)-based real-time simulator that is developed based on the concept of simulators hardware reconfigurability (i.e., to change the underlying hardware architecture of the simulator to accommodate various power system topologies). The uniqueness of the RH-RTS is the underlying hardware architecture. The RH-RTS has a massively parallel customized hardware architecture that is tailored to the solution of the mathematical model of the power system under consideration. The RH-RTS enables the simulation of large power systems with a computation-time per simulation time-step in the range of tens of nanoseconds. Not only does the RH-RTS provide a means for real-time operation (e.g., for closed-loop testing of physical control/protection platforms in hardware-in-the-loop (HIL) configuration), it also provides a means for faster-than-real-time operation (e.g., for statistical switching studies). This paper provides validation and evaluation of the performance of the RH-RTS. This paper presents a case study involving the simulation of a power system in both real time and faster than real time. The computation time per simulation time-step is as low as 24 ns, for realistic size systems, which is, by far, the lowest computation time reported in the technical literature.
Published Version
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