The quality-control test of the digital logic for the ATLAS new small wheel read-out controller ASIC

Abstract

The Read-Out Controller (ROC) ASIC is an on-detector custom real-time data packet processor for the upgraded New Small Wheel (NSW) Trigger and Data Acquisition (TDAQ) system of the ATLAS Experiment at CERN, Geneva. The ROC is a highly-configurable data concentrator that allows the optimization of bandwidth utilization, reduces the required number of data links, minimizes data loss, implements congestion and flow control mechanisms, allows data filtering, supplies phase adjustable clock signals and offers relatively larger buffer spaces for the readout system. The paper details the designed, implemented and deployed FPGA-based test setup for the quality-control of the ROC packet processing logic. The FPGA-based test setup emulates the ROC context using firmware-based input data streams emulators and output data analyzers which are controlled and monitored by a soft-core Xilinx MicroBlaze microprocessor instantiated on the same FPGA. The ROC chip is accommodated on a custom PCB which assures the power supply and the interface to the FPGA. A mathematical model of the ROC performance as a function of its configuration and input data throughput is proposed. The ROC digital design was successfully validated and its performance assessed, confirming the theoretical model. The design coverage, test procedure and partial mass-testing results are presented and analyzed.