The QP Triangle: A Graphical Method for Bias Design

Abstract

A graphical design procedure is presented based upon a QP triangle for the design of bipolar transistor (BJT) bias circuits. The design technique stresses quiescent point (QP) location on the IC-VCE characteristics and considers the effects of simultaneous variations in the BJT parameters hFE, VBE, and ICO upon QP location. The QP triangle method is developed for the standard one-battery BJT CE stage discussed in many introductory electronic circuits textbooks. The QP triangle method is applied to a specific CE stage which has to meet certain design specifications. One important specification is that the circuit must operate over the temperature range 25-100°C with silicon N-P-N BJT's having values of h<FE (25°C) > 40 and hFE 100°C) < 200. The available tradeoffs between the peak-to-peak voltage Vpp and the current gain AI are stressed and the best available design is selected. The performance of the selected design was simulated on a digital computer and measured in the laboratory. Both the computer simulation and the experiment are in good agreement with the design. The QP triangle method has been used in an introductory electronic circuits course with success for several years. Students understand this graphical design procedure and are able to apply it. It is recommended for beginning electronics students. An interactive computer program AMPDSN to aid students and instructors design the standard one-battery BJT CE stage is also described. An algorithm based upon the QP triangle is used. The program language is Basic.