Abstract
The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller beam pipe at a radius of 3.3 cm. To cope with the high radiation and hit occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as well as the experience in its construction will be presented, focusing on adopted technologies, module and staves production, qualification of assembly procedure, integration of staves around the beam pipe and commissioning of the detector.
Highlights
The initial Pixel Detector is designed to operate at peak instantaneous luminosities of up to 1×1034 cm−2s−1 and performed very well during LHC Run-1 with tracking efficiency of 99% and spatial
For Run-2 the pixel detector has to cope with increasing instantaneous luminosity and pile-up of >50 collisions per bunchcrossing
The pixel detector has a key role in the data analysis as it provides primary and secondary
Summary
The IBL double-chip module uses planar n-in-n silicon sensors similar to the outer layers, the inactive edges are significantly reduced, which allows to maximise the acceptance area without complex z-overlapping design. Each planar sensor carries two FE-I4 readout chips with 80 columns and 336 rows of pixels each. The IBL single-chip module uses a 3D silicon sensors, with a double column design of vertical electrodes with 50μm pitch. Prior to bump-bonding the FE-I4 is thinned to 150μm. The sensor-FE-I4 assembly is completed to a module by gluing a thin Cu-kapton flex circuit on the sensor back-plane side, which is wire bonded to all chip and sensor connections. The yield of accepted modules for planar modules is 75% and for 3D modules 63% after initial bump-bonding difficulties were resolved
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