The pipeline bus: An interconnection network for multiprocessor systems

Abstract

The design of a network switch for synchronously clocked packet switching networks is presented. The switch includes the node interface and logic handling of the arbitration and routing for a large class of network topologies, namely n-dimensional rectangular grids including hypercubes and other highly efficient topologies. In the context of the SUPRENUM project the paper concentrates on two-dimensional meshes. Routing, arbitration, blocking, and fault tolerance issues are discussed.