The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes

Abstract

In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrial-based experiments demonstrate the beneficial impact of metal-fill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation.