Abstract
The potential and restrictions of cryogenic SOI technologies are reviewed. First the low temperature device operation, illustrated by extensive experimental data covering a broad temperature range down to liquid helium, is discussed in order to validate the theoretical models. Attention is given to the kink phenomenon, transient and hysteresis effects, the device breakdown and latch‐up behavior, and the noise performance. Several design methodologies and technological modifications for eliminating the cryogenic artifacts are critically discussed. Alternative device concepts such as the twin‐transistor structure and the gate‐all‐around concept are also addressed. Finally some considerations for digital and analog circuit applications are given in view of the future perspectives of cryogenic SOI CMOS technologies.
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