The Passive DOA Estimation by Virtual Time Reversal on FPGA

Abstract

The Virtual Time Reversal algorithm has the advantages of low computational complexity and high accuracy in low signal-to-noise ratio, so it is easy to implement in hardware engineering. The parallel design of FPGA can greatly improve the speed of direction finding system and satisfy the real-time direction finding. The paper adopts Virtex-7 FPGA of Xilinx Company with Verilog-HDL to program the design of Passive DOA Estimation by Virtual Time Reversal (PVTR-DOA). Firstly, according to the principle of Virtual Time Reversal algorithm, a parallel processing scheme is proposed. This design establishes the algorithm module through Vivado software platform, and uses package IP tool to package the algorithm module into a custom IP core. Then, the data to be tested in DDR3 and the custom IP core are moved through DMA data interaction mode for signal processing. The FPGA design uses MicroBlaze core to implant C code on SDK platform to control the embedded system. Finally, the effectiveness and real-time direction finding of the hardware design are verified by the experimental results.