The new line in IC design

Abstract

If deep submicron ICs are to excel in yields and performance, the design process must focus throughout on their interconnects. A new design process grapples with the problem. Design For interconnectivity, as it is called, ensures that interconnection information is available throughout the design process, so that the circuitry may be optimized around it at every stage. The availability of this information proves the key to achieving yield and performance goals in deep submicron designs. The novel process involves predicting, at an early stage in logic design, the probable paths of interconnects and any problems likely to ensue. Later on, it tackles device layout and performance verification one small step at a time. To do this, the front-end logic designers need tools to gather the proper information without plunging into the intricacies of physical design, while the back-end physical designers need tools with which to surmount interconnect issues. Moreover, technologies are required to produce globally optimized results by linking logical and physical design tools more closely.