The new LHCb trigger and DAQ strategy: a system architecture based on gigabit-ethernet

Abstract

The LHCb software trigger has two levels: a high-speed trigger running at 1 MHz with strictly limited latency and a second level running below 40 kHz without latency limitations. The trigger strategy requires full flexibility in the distribution of the installed CPU power to the two software trigger levels because of the unknown background levels and event topology distribution at the time the LHC accelerator will start its operation. This requirement suggests using a common CPU farm for both trigger levels fed by a common data acquisition (DAQ) infrastructure. The limited latency budget of the first level of software trigger has an impact on the organization of the CPU farm performing the trigger function for optimal usage of the installed CPU power. We will present the architecture and the design of the hardware infrastructure for the entire LHCb software triggering system based on Ethernet as link technology that fulfills these requirements. The performance of the event-building of the combined traffic of both software trigger levels, as well as the expected scale of the system will be presented.