Abstract
An architectural summary of the AN/UYS-2 multi-processor digital signal processor is presented along with a brief description of the major technologies that are being incorporated into it. Discussion concentrates on the AN/UYS-2's implementation of data-flow parallel processing to achieve exceptionally high computing throughput rates. In addition, its functional components and the implementation of its hardware functional elements into standard electronic modules are discussed. Supporting this multi-processor architecture is a signal processing graph language methodology called Processing Graph Methodology (PGM) which is used to efficiently and cost-effectively program the AN/UYS-2. Finally, follow-on candidate technologies for infusion into the AN/UYS-2 are highlighted.
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