The Navy's new standard digital signal processor, the AN/UYS-2

Abstract

Current Navy signal processing requirements range from tens of millions to hundreds of millions of multiply-add operations per second. It is expected that these requirements will increase tenfold within the next ten years. To accommodate these expanding requirements, the Navy is building the Signal Processor (AN/UYS-2). The AN/UYS-2 design is driven by the fact that it is the Navy standard signal processor. Being a stantard, it must satisfy more requirements than just high throughput. It must be programmable, modular, expandable, flexible supportable, reliable and provide this capability for the next 20 years to support existing and future users. In order to make it programmable (and therefore reduce the total life cycle ownership cost), the AN/UYS-2 utilizes a Navy developed signal processing graph language methodology called PGM. The implementation of PGM on AN/UYS-2, provides the AN/UYS-2 user with a convenient and cost effective way of specifying the signal proccessing algorithms to be executed for a given application. The AN/UYS-2 desgin approach is to implement PGM and to develop a modular, multiprocessor that could meet a wide range of air, sea, and shore signal processing applications. In order to meet this requirement, a hybrid control-flow/data-flow architecture was chosen to enable evolutionary technology infusion. VLSI component technology is required to implement the primary processing engine in the architecture. The AN/UYS-2 architecture consists of a variable combination of multiple types of Functional Elements (FEs), a data transfer network, a control bus, and a built-in-test (BIT) control bus. This paper provides a review of AN/UYS-2 basic design and growth potential.