The Motorola DSP96002 IEEE Floating-point Digital Signal Processor

Abstract

The Motorola DSP96002 is a general- purpose digital signal processor which implements the IEEE 754-1985 Standard for Binary Floating-point Arithmetic [I 1. Its 32-bit architecture, combined with unique enhancements for digital signal processing (DSP) applications result in a peak performance of 13.5 million instructions per second (MIPS) and 40.5 million floating-point operations per second (MFLOPS) with a 27 MHz clock. Average performance on typical benchmarksis 13 MIPS and j8 MFLOPS. The DSP96002 has extensive multiprocessing support, which allows multiple 96002's to deliver hundreds or thousands of MFLOPS in a compact, low-power system. The processor has dual external buses, each with separate 32-bit address, 32-bit data, bus control and arbitration ports. Each bus has on-chip support for multiprocessor communications, the fast access modes of DRAM/VRAM memories and interfaces to non-96002 processor buses. Based on a superset of Motorola's fixedpoint DSP56000/1 [2] the DSP96002 provides software compatibility with DSP5dOOO/l source code.. The high parallelism in the central processing unit (CPU), combined with two independent DMA contro.llers, on-board ROM and RAM, and 1/0 in a high level of integration creates a powerful single-chip computing node for parallel processing systems.