The Michelangelo step: removing scalloping and tapering effects in high aspect ratio through silicon vias

Simone Frasca,Benoît Pasquier,Edoardo Charbon,Ivo N Arabadzhiev,Grégoire F M Tomassi,Rebecca C Leghziel,Sandro Carrara

doi:10.1038/s41598-021-83546-w

Simone Frasca, Benoît Pasquier + Show 5 more

Open Access

https://doi.org/10.1038/s41598-021-83546-w

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Journal: Scientific Reports	Publication Date: Feb 17, 2021
Citations: 12	License type: open-access

Affiliation: École Polytechnique Fédérale de Lausanne

Abstract

We present here, for the first time, a fabrication technique that allows manufacturing scallop free,non-tapered, high aspect ratio in through-silicon vias (TSVs) on silicon wafers. TSVs are among major technology players in modern high-volume manufacturing as they enable 3D chip integration. However, the usual standardized TSV fabrication process has to deal with scalloping, an imperfection in the sidewalls caused by the deep reactive ion etching. The presence of scalloping causes stress and field concentration in the dielectric barrier, thereby dramatically impacting the following TSV filling step, which is performed by means of electrochemical plating. So, we propose here a new scallop free and non-tapered approach to overcome this challenge by adding a new step to the standard TSV procedure exploiting the crystalline orientation of silicon wafers. Thank to this new step, that we called “Michelangelo”, we obtained an extremely well polishing of the TSV holes, by reaching atomic-level smoothness and a record aspect ratio of 28:1. The Michelangelo step will thus drastically reduce the footprint of 3D structures and will allow unprecedented efficiency in 3D chip integration.

Highlights

We present here, for the first time, a fabrication technique that allows manufacturing scallop free, non-tapered, high aspect ratio in through-silicon vias (TSVs) on silicon wafers
TSV fabrication can be categorized based on the steps relative to the complementary metal–oxide–semiconductor (CMOS) fabrication process, such as: via first, if the TSV is formed before the CMOS process, via middle, if the TSV is formed after the devices but before the metal layers, and via last, where the TSV is fabricated after completing all the steps of classical CMOS p rocesses[1]
The depth obtained after the deep reactive ion etching was not equal for all hole sizes because the etching rate slows down with increasing aspect ratio: this effect is commonly known as Aspect Ratio Dependent Etching[21]

Summary

Introduction

For the first time, a fabrication technique that allows manufacturing scallop free, non-tapered, high aspect ratio in through-silicon vias (TSVs) on silicon wafers. We propose here a new scallop free and non-tapered approach to overcome this challenge by adding a new step to the standard TSV procedure exploiting the crystalline orientation of silicon wafers. Thank to this new step, that we called “Michelangelo”, we obtained an extremely well polishing of the TSV holes, by reaching atomiclevel smoothness and a record aspect ratio of 28:1. The semiconductor community has shifted towards 3D integration to achieve higher electrical component density and increased performance In this context, one of the most promising technologies is the through-silicon via (TSV)[1]. In 2007, Toshiba released a CMOS Image sensor which was the first commercial product with TSV incorporated in a batch product, and this boosted the growth of 3D integration[4]

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