Abstract

Summary form only given: The large-scale hard combinatorial optimization problems arise in many areas. One of them is Physical Design Automation. Such problems as partitioning, packaging, placement, routing, compaction are very hard. From mathematical point of view, these problems belong to the intractable combinatorial - NP-class. Optimization is especially important for VLSI, SoC and NoC design. The complication of the electronic circuit requires a further search for the new efficient, effective and robust approaches to solve such problems with high quality. Nowadays, chips have billions of transistors. Many of these kinds of problems are connected with the usage of identical input data. The idea of how to solve such problems is to transfer the full mathematical model to the aggregate mathematical notation, which could significantly decrease the number of arguments, and rather than operating with the original elements, the number of which is extraordinarily high, deal with the macromodels of essentially smaller number parameters. It enables us not only to decrease the size of the problem, facilitating the solution and reducing the calculation consumption, but also to considerably improve the the solutions quality and to trap into the zone of the global optimum much more easily. The algorithms presented in this tutorial have some new properties: (a) can be efficient in choosing the most appropriate number of partitions to divide the circuit; (b) the arbitrary division ratio can be chosen for partitioning; (c) the same procedures can be used for the initial solution finding and its optimization in partitioning and placement; (d) the topological and flexible routing algorithms are appropriate for the arbitrary surface shapes and placed components, arbitrary angles and routes with arbitrary width and guarantee the best quality and high routability; (e) close to linear computational complexity; (f) provide high quality of the solutions; (g) are appropriate for the large and very large-scale problems.

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