The method for constructing fault-tolerant photonic switches for high-performance computing systems

Abstract

In this paper the new type of fault-tolerant non-blocking photonic switch is presented for the first time. The proposed switch architecture is based on quasi-complete graph topology which use provides non-blocking and fault-tolerant switching process. The new two-stage switch architecture uses the stage of dual photonic switches and pairs of photonic demultiplexers and multiplexers which have been described in detail by authors in their previous works. Depending on the number of different backup connections, the two types of fault-tolerant pho-tonic switches are considered in this paper: single-channel fault-tolerant photonic switch and dual-channel fault-tolerant photonic switch. The mathematical expressions for calculating the switching and fiber complexities of these two types of fault-tolerant photonic switches are also presented here for the first time. The numerical calculations shown that the increasing the reliability of the fault-tolerant photonic switches twice leads to an increasing their switching complexity in 1.4 times and fiber complexity in 1.8 times.