The Magic Rule of Tiles: Virtual Delay Insensitivity

Abstract

Delay-insensitivity is a theoretically attractive design principle which helps circuits to be resistant to process variations, particularly exhibiting them selves at the system level as delay variations. Unfortunately, delay insensitive (DI) design is impractical for most real systems. Speed independent (SI) design is often used in practice as a next best approach. With the scaling of wires becom ing more and more difficult compared with logic gates at current and future technology nodes, SI systems are becoming less acceptable as “approximates” for DI systems. This paper proposes an approach based on decomposing complex systems into simple, manageable blocks which can be safely rendered in an SI manner. These blocks are then connected using interconnects which satisfy DI requirements to obtain “virtual DI” behaviour at system level. We demonstrate this approach with a tile-based implementation of a multi-access arbiter.