The Local Wavelet Transform: a memory-efficient, high-speed architecture optimized to a Region-Oriented Zero-Tree coder

Abstract

The memory required for the implementation of the 2D wavelet transform typically incurs relatively high power consumption and limits the speed performances. In this paper we propose an optimized architecture of the 1D/2D wavelet transform, that reduces the memory size cost with one order of magnitu de compared to classical implementation styles. This so-called Local Wavelet Transform also minimizes the memory access cost, thanks to its spatially localized processing. Furthermore, the proposed architecture introduces concurrency in the data transfer mechanism, resulting in speed performances that are not limited by data transfer delays to/from main (off-chip) memory. Finally, the production of parent-children trees in indivisible clusters, makes an easy interfacing to Zero-Tree encoder modules possible, while keeping Region-of-Interest functionalities. Practical implementations of the 1D and 2D Local Wavelet Transform with up to 9/7-tap wavelet filters and a large number of levels (e.g. 4, 5), can process 10 Msamples/s, with an internal processing clock of 40 MHz, in a very modest 0.7 μm CMOS process.