Abstract
Program logics and semantics tell a pleasant story about sequential composition: when executing (S1;S2), we first execute S1 then S2. To improve performance, however, processors execute instructions out of order, and compilers reorder programs even more dramatically. By design, single-threaded systems cannot observe these reorderings; however, multiple-threaded systems can, making the story considerably less pleasant. A formal attempt to understand the resulting mess is known as a “relaxed memory model.” Prior models either fail to address sequential composition directly, or overly restrict processors and compilers, or permit nonsense thin-air behaviors which are unobservable in practice. To support sequential composition while targeting modern hardware, we enrich the standard event-based approach with preconditions and families of predicate transformers. When calculating the meaning of (S1; S2), the predicate transformer applied to the precondition of an event e from S2 is chosen based on the set of events in S1 upon which e depends. We apply this approach to two existing memory models.
Highlights
Sequentiality is a leaky abstraction [Spolsky 2002]
We show that Pomsets with Preconditions (PwP) can be extended with families of predicate transformers (PwT) to calculate sequential dependencies in a way that is compositional and direct: compositional in that the denotation of (S1; S2) can be computed from the denotation of S1 and the denotation of S2, and direct in that these can be calculated independently
The compiler could reorder the read of x and write to y, allowing both reads to see 1. Attempting to generate this execution with syntactic dependencies, results in the following candidate execution, which has a cycle and is disallowed: To address this, Jagadeesan et al [2020] introduced Pomsets with Preconditions (PwP), where events are labeled with logical formulae
Summary
Sequentiality is a leaky abstraction [Spolsky 2002]. For example, sequentiality tells us that when executing (r1 := x ; y := r2), the assignment r1 := x is executed before y := r2. It is surprising difficult to define a model that allows common compiler optimizations and hardware reorderings yet disallows nonsense behaviors that don’t arise in practice. The latter are commonly known as “thin-air” behaviors [Batty et al 2015]. These axioms use existentially defined global relations, such as memory order (mo), which must be a per-location total order on write actions Part of this non-compositionality is essential: In a concurrent system, the complete set of writes is known only at top-level. Supplementary material for this paper is available at https://weakmemory.github.io/pwt
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