The Layout Geometry and Power-Level Dependences of Degradation in Complementary Metal–Oxide–Semiconductor RF Power Cells from Hot-Carrier Stress with Load Pull System

Abstract

A comparison of reliability for 0.18-µm complementary metal–oxide–semiconductor (CMOS) power cells with different layout geometry and output power level is proposed. The layout geometries of power cell are designed and optimized to alleviate hot-carrier effects for better performance and reliability. The degradation induced by the reflected power from load mismatch is demonstrated. The hot-carrier effect is aggravated by load mismatch in high power operation. The degree of degradation depends on input power levels. Two sets of power cells for output power of 10 and 50 mW are measured in this work. The results show that the drain current of the cell with compact layout was degraded much more critically after RF stress than one with dispersive layout pattern. Otherwise, both the degradation from DC and RF stress was higher in the cells with higher output power-level.