Abstract
Partial reconfiguration is a technology that the different bitstream is loaded into reconfigurable region to realize the different functions. Partial reconfiguration be able to make reconfigurable time shorten greatly and implement time division multiplex access of logic resources. JTAG (Joint Test Action Group) is an essential module of FPGA (Field Programmable Gate Array), accomplishing testing, configuration and soon. As the result of supporting user-defined instruction, JTAG circuit has the good extensibility. In order to implement partial reconfiguration of logic resources, this paper puts forward dynamic reconfiguration instruction-DRP, and designs the JTAG circuit of accomplishing dynamic reconfiguration.
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