The investigation of DARC etch back in DRAM capacitor oxide mask opening

Abstract

Opening the silicon oxide mask of a capacitor in dynamic random access memory is a critical process on a capacitive coupled plasma (CCP) etch tool. Three steps, dielectric anti-reflective coating (DARC) etch back, silicon oxide etch and strip, are contained. To acquire good performance, such as low leakage current and high capacitance, for further fabricating capacitors, we should firstly optimize DARC etch back. We developed some experiments, focusing on etch time and chemistry, to evaluate the profile of a silicon oxide mask, DARC remain and critical dimension. The result shows that etch back time should be controlled in the range from 50 to 60 s, based on the current equipment and condition. It will make B/T ratio higher than 70% meanwhile resolve the DARC remain issue. We also found that CH2F2 flow should be ~15 sccm to avoid reversed CD trend and keep inline CD.