Abstract
The paper explores a number of possible hardware architectures for implementing synchronous dataflow (SDF) models of digital signal processing (DSP) applications in reconfigurable logic components, for example, Field Programmable Gate Arrays (FPGAs). The objective is to produce efficient hardware implementations of SDF graphs by exploiting the parallelism inherent in most graphs whilst taking advantage of the reconfigurable aspects of the target architecture. Classic area/performance tradeoffs can be made in order to meet the requirements of DSP applications.
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