Abstract
Loop pipelining usually leads to significant performance improvements in coarse-grained reconfigurable architectures. Loop scheduling methods,synchronization of pipelines and measures efficiently utilizing the memory bandwidth are the key issues of loop pipelining techniques. This paper introduces the implementation of loop self-pipelining with supports in hardware on LEAP,which based on the hardware supporting automatically loop-iteration scheduling,data-driven ALU and configurable switch routers. Taking the advantages of dynamically scheduling iteration operations,LEAP exploits high degree of parallelisms. With the help of distributed memory access and efficiently data reusing of producer-consumer between computing elements,LEAP improves the bandwidth utilization. The experimental results show that the speedup over general processor can reach 13.08 to 535.22.
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