The impacts of control gate voltage on the cycling endurance of split gate flash memory

Abstract

In this paper, the "erase" degradation in program/erase (P/E) cycling endurance of split-gate flash memory has been investigated. It is found that increasing the control-gate (CG) voltage (V/sub CG/) during erasing can slow down the "window closure" of cycling endurance since a higher V/sub CG/ can "push" the FG potential into gradual part of I/sub Read-out/-V/sub FG/ curve and in turn reduce the read-out current degradation. Moreover, the experimental results show that scaling down the gate oxide thickness under FG can effectively reduce the I/sub Read-out/ degradation in the cycling endurance test.