The impact of tolerance on kill ratio estimation for memory

Abstract

Spatially correlating in-line inspection data and post process electrical test data is an effective approach for estimating the yield impact of different defect types and/or process steps. An estimator for the probability that a particular type of defect kills an electrically testable structure, the kill ratio, has been described in the literature. This estimator may be used to predict the yield impact immediately after inspection, providing a number of benefits. It may also be used to generate a yield loss pareto by defect type. This paper introduces a new estimator for the kill ratio, which takes into account the impact of tolerance, a parameter setting the maximum distance between a defect and structure under which they are considered spatially correlated. This estimator was developed for memory (bitmap) data, where the tolerance is very large relative to the size of the structure. The tolerance is often increased to accommodate for misalignment between inspection tool sets and the electrical data. The problem with increasing the tolerance is that the chance of coincidental correlation between failed bits and defects increases as the square of tolerance. Analytical and simulation results are presented to illustrate the danger of using the existing kill ratio estimator with too large a tolerance or overly sensitive inspection tool recipes. These same results illustrate the improved performance of the new estimator. Because the number of falsely attributed defects adds up over a number of inspections, a small error in the kill ratio estimator can have a major impact on the yield loss pareto.