The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance

Abstract

In this paper, the analogue performance of a 65nm node double gate SOI (DGSOI) is qualitatively investigated using MixedMode simulation. The intrinsic resistance of the device is optimised by evaluating the impact of the source/drain engineering using variation of spacers and doping profile on the RF key figures of merit such as fT, and fMAX. It is evident that longer spacers, which approach the length of the gate offer better RF performance irrespective of the profile as long as the doping gradient at the gate edge is <7nm/decade. Analytical expressions, which reflect the dependence of fT, and fMAX on extrinsic source, drain and gate resistances RS, RD and RG have been derived. While RD and RS have equal effect on fT, RD appears to be more influential than RS in reducing fMAX. The sensitivity of fMAX to RS and RD. has been shown to be greater than to RG.