The Impact of Soft Error Event Topography on the Reliability of Computer Memories

Abstract

The frequency, nature, and scope of Soft Error Events (SEEs) is becoming an increasingly significant reliability concern as transistors continuously scale down into ever smaller nanometer memory chip geometries. As part of the on-going research efforts required to address this steadily developing situation, two significant research questions were addressed by the research work presented within this paper. The first research question addressed the possibility of crafting a novel methodology whose application would consistently lead to the creation of viable Monte Carlo SEE Simulators. Each of these Monte Carlo SEE Simulators would need to be capable of adequately profiling SEEs as well as simulating and modeling their impacts on the reliability of a variety of simulated 45-nm SRAM computer memories. The Standard 2-Parameter Weibull Soft Error Event (S2P-WSE) Simulator proposed within this paper as a direct application of this novel methodology successfully produced simulation results that were comparatively equivalent both directly and statistically to the results calculated by the empirically validated Weibull Row-Clustered Soft Error Reliability (WRCSER) model. This WRCSER Model was independently developed and empirically validated against proprietary reliability datasets obtained from testing a CISCO 45-nm SRAM computer memory device in a laboratory setting. The S2P-WSE Simulator itself was validated by means of a Kruskal-Wallis ANOVA test and by direct comparison of both the model and the simulator as a function of their respective failure probability and reliability results on 45-nm SRAM simulated computer memory devices subjected to the same SEE impacts over the course of an entire simulation run. The second research question sought to determine the significance of SEE topography versus a Row-Depth-Only bit error severity assumption on the reliability of simulated 45-nm SRAM computer memories shielded from the accumulating impacts of SEEs by variable error-correction codes, row-depth interleaving distances, and periodic scrubbing time intervals. The simulation runs for both the S2P-WSE Simulator and the T2P-WSE Simulator were carefully setup to ensure that only the potentially divergent factor between the results generated by the two simulators was the T2P-WSE Simulator's stochastically estimated topographical shape for each SEE impacting the simulated computer memory device. The work within this paper successfully demonstrated through direct plots of the two simulators' failure probability and reliability results and the results of the Kruskal-Wallis ANOVA tests that the topography of SEEs does represent a significant impact on the overall failure probability and reliability of 45-nm SRAM computer memory devices.