The impact of mixed negative bias temperature instability and hot carrier stress on single oxide defects

Abstract

Even though transistors are rarely subjected to idealized bias temperature instability or hot carrier stress conditions in circuits, there is only a limited number of studies available on mixed bias temperature instability and hot carrier stress. Here we summarize the results of the first study of mixed negative bias temperature instability and hot carrier stress (drain stress voltage |Vstr D |> 0 V and gate stress voltage |Vstr D | ≥ |V DD |) at the single oxide defect level in nano-scale SiON pMOSFETs. We found that less defects contribute to a threshold voltage shift ΔV th during recovery and thus to the recoverable degradation than would be expected from a simple electrostatic model. Time-dependent defect spectroscopy measurements show that even defects at the source side of the oxide can remain neutral after mixed negative bias temperature instability and hot carrier stress although they are fully charged after homogeneous negative bias temperature instability stress. As a consequence, they do not contribute to a ΔV th drift after mixed negative bias temperature instability and hot carrier stress. We show that this unexpected reduction in the defect's occupancy can be consistently explained by non-equilibrium processes induced by the large drain voltage such as impact ionization.