Abstract
The High Luminosity Large Hadron Collider (HL-LHC) at CERN will constitute a new frontier for the particle physics after the year 2027. Experiments will undertake a major upgrade in order to stand this challenge: the use of innovative sensors and electronics will have a main role in this. This paper describes the recent developments in 65 nm CMOS technology for readout ASIC chips in future High Energy Physics (HEP) experiments. These allow unprecedented performance in terms of speed, noise, power consumption and granularity of the tracking detectors.
Highlights
Microelectronics has always played a fundamental role in high energy particle physics research
The ETROC [21] is the readout ASIC in 65 nm technology foreseen as front-end for the Low Gain Avalanche Detector (LGAD) sensor pixel of the MIP Timing Detector (MTD) detector of CMS
A comparison on the essential technical specifications of low power GigaBit Transceiver (lpGBT) and GBT is shown in Table 3 showing the considerable improvements made in high speed data links for High Energy Physics (HEP) experiments with the use of 65 nm CMOS technology
Summary
Microelectronics has always played a fundamental role in high energy particle physics research. A big boost was the formation of a specific R&D international collaboration, called RD531, and of a few projects as [1] or AIDA20202, all bringing together several experts to leverage this technology for HEP This has allowed the achievement of considerable progress in several areas: understanding the radiation hardness of the technology; development of basic building blocks (DAC, ADC, Band-Gap, T-sensors, PLL, cable-driver, power-regulators, memory-cells, TDC, high-speed serializer); design of small, low power, fast analog front-ends; development of complex digital circuits; the application of Single Event Upset (SEU) mitigation techniques and their verification on real chips; the integration of large-size ASIC, with complex digital logic, I/O.
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