The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits

Abstract

The yield of low voltage digital circuits is found to be sensitive to local gate delay variations due to uncorrelated intra-die parameter deviations. Caused by statistical deviations of the doping concentration they lead to more pronounced delay variations for minimum transistor sizes. Their influence on path delays in digital circuits is verified using a carry select adder test circuit fabricated in 0.5 /spl mu/m CMOS technologies with two different threshold voltages. The increase of the path delay variations for smaller device dimensions and reduced supply voltages as well as the dependence on the path length is shown. It is found that for circuits with a large number of critical paths with a low logic depth are most sensitive to uncorrelated gate delay variations. Scenarios for future technologies show the increased impact of uncorrelated delay variations on digital design. A reduction of the maximal clock frequency of 9% is found for highly pipelined systems realized in a 0.18 /spl mu/m CMOS technology.