Abstract

This paper presents the method and results of a study on the impact of back-end-of-line (BEOL) process variations on the interconnect properties and therefore on the timing of critical paths of low-power circuits at the 45-nm technology node. Three critical paths with different routing styles are considered. At sub-100nm dimensions, the so-called narrow-line effect (Steinhoegl et al., 2003) appears, which translates relatively small variations in interconnect geometry into a much larger variation in interconnect resistance. However, the interconnect resistance and capacitance fluctuate in opposite directions minimizing the detrimental effect of BEOL process variations on timing of the critical paths. Even when the interconnect resistance varies greatly (25% 1sigma) due to the BEOL process variations, only a small spread (< 5% 1sigma) of the path timing is observed for all considered routing styles

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