The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET

Abstract

In this paper, through TCAD simulations, we show that the introduction of a thin paraelectric (PE) layer between the ferroelectric (FE) and dielectric (DE) layers in an MFIS structure, expands the design space for the FE layer enabling hysteresis-free and steep subthreshold behavior, even with a thicker FE layer. This can be explained by analyzing the FE-PE stack from a capacitance perspective where the thickness of the PE layer in the FE-PE stack has the effect of reducing the FE layer thickness, while also reducing the remnant polarization. Finally, for the same FE-PE-DE stack, analog performance parameters such as \(\frac {G_{m}}{G_{ds}}\) and \(\frac {G_{m}}{I_{d}}\) are analyzed, showing good characteristics over a wide range of gate lengths, at low drain voltages, thus demonstrating applicability for low power applications.