The hype, myths, and realities of testing 2.5D/3D integrated circuits

Abstract

Despite the numerous benefits offered by 2.5D/3D integration, testing remains a major obstacle that hinders its widespread adoption. Concerns related to test cost, yield and reliability continue to derail the commercial exploitation of 2.5D/3D ICs. Test techniques and design-for-testability (DfT) solutions are now being explored in the research community, with considerable focus on wafer probing, pre-bond test of passive interposers, test access to modules in stacked dies, cost modeling, and the targeting of new defect types. In this talk, the speaker will examine the hype, myths, and realities of 2.5D/3D ICs. He will reflect on some of the over-hyped claims and expose the many myths that have been exposed in recent years. He will present a reality-check on testing and DfT challenges, and describe some of the recent solutions being advocated for these challenges. The key questions to be addressed are: What to How to When to Test? To answer these questions, the presentation will cover pre-bond testing of TSVs and interposers, DfT solutions and optimization for stack testing, and test-flow selection.