The Helix switch: a single chip cell switch design

Abstract

A VLSI architecture for a high speed, non-blocking, cell switch is proposed. The architecture is particularly well suited for VLSI implementation, and is scalable to support many connections at high data rates. The switch employs a self-routing shift register ring design to transfer cells between the inputs and the outputs, and utilizes an efficient shared buffer scheme at the output. The shift register ring design is advantageous from a VLSI standpoint because it uses short interconnections, low fan-out for the gates, and very few levels of logic, thus reducing the delay, and area; a critical requirement for a high bandwidth switch. Furthermore, the switch is designed using dynamic latches which require very small area. Thus, the shift register ring provides a compact, low delay interconnection fabric for high throughput switching. Since the shift register ring serializes (pipelines) the delivery of cells to the destination, the concurrent cells destined for the same output arrive in an interleaved fashion. Thus, the Helix switch resolves output contention by serializing the delivery of cells without impacting performance. Furthermore, the ring design is a very effective means of supporting multicast and broadcast. The details of the implementation and performance evaluation of a single-chip VLSI design of a 16-port (1Gbps/s per port) ATM switch, based on the Helix architecture, are presented in this paper.