The Hardware and Signal Processing Architecture of LabPET™, a Small Animal APD-Based Digital PET Scanner

Abstract

The highly multiplexed analog processing front-end of current Positron Emission Tomography (PET) scanners yields high accuracy for timing but adds significant dead time and offers little flexibility for improvement. A new fully digital APD-based scanner architecture is proposed wherein nuclear pulses are sampled directly at the output of the Charge Sensitive Preamplifier (CSP) with one free-running ADC per channel. This approach offers the opportunity to explore new digital signal processing algorithms borrowed from other fields like command and control theory, as well as advanced heuristics such as neural networks. The analog front-end consists of a dedicated 0.18- mum, 16-channel CMOS charge sensitive preamplifier. Digitization is performed with off-the-shelf dual 8-bit analog-to-digital converters running at 45-MSPS. Digital processing is shared between a FPGA and a Digital Signal Processor (DSP), which can process the data from up to 64 parallel channels without dead time. The FPGA deals with the initial signal analysis for energy measurement and time stamping, while crystal identification is deferred to the DSP running computation-intensive recursive algorithms. The entire system is controlled serially through a Firewire link by a Graphic User Interface. The initial LabPETtrade implementation of the system is a dedicated small animal scanner holding up to 4608 APD channels at an averaged count rate of up to 10 000 events/s each.