The growth of low-threading-dislocation-density GaAs buffer layers on Si substrates

Abstract

Monolithic integration of III–V optoelectronic devices on Si platform is gaining momentum, since it enables advantages of low cost, less complexity and high yield for mass production. With the aim of achieving advances in monolithic integration, the challenges associated with lattice mismatch between III–V layers and Si substrates must be overcome, as a low density of threading dislocations (TDs) is a prerequisite for the robustness of the integrated devices. In this paper, we have investigated and compare different types of dislocation filter layers (DFLs) from InGaAs asymmetric step-graded buffer layer (ASG), InGaAs/GaAs strained-layer superlattices, and quaternary alloy InAlGaAs ASG, on the functionality of reducing TD density (TDD) for GaAs buffer layers on Si. Compared to other DFLs, the sample with InAlGaAs ASG buffer layer shows the lowest average TDD value and roughness, while the decrease of TDD in the sample with InAlGaAs ASG buffer layer can be understood in terms of the hardening agent role of aluminium in the InAlGaAs ASG. By further optimising the InAlGaAs ASG through thermal cyclic annealing, we successfully demonstrate a low surface TDD of 6.3 ± 0.1 × 106 cm−2 for a 2 μm GaAs/InAlGaAs ASG buffer layer grown on Si. These results could provide a thin buffer design for monolithic integration of various III–V devices on Si substrates.