Abstract
The Giga Bit Transceiver based Expandable Front-End (GEFE) is a multi-purpose FPGA-based radiation tolerant card. It is foreseen to be the new standard FMC carrier for digital front-end applications in the CERN BE-BI group. Its intended use ranges from fast data acquisition systems to slow control installed close to the beamlines, in a radioactive environment exposed to total ionizing doses of up to 750 Gy. This paper introduces the architecture of the GEFE, its features as well as examples of its application in different setups.
Highlights
This paper introduces the architecture of the Giga Bit Transceiver based Expandable Front-End (GEFE), its features as well as examples of its application in different setups
In GEFE, the high-speed lines (DP) of the FMC HPC connector do not comply with the ANSI/VITA 57.1, since they are used as user-specific I/Os and can be used for special functions (e.g. Slow Control (SC) e-link to FMC HPC, ProAsic3 FPGA programming from JTAG master on FMC, etc.)
This paper has introduced the GEFE, a multi-purpose FPGA-based radiation tolerant card available under the CERN Open Hardware License, which is foreseen to be the new standard FMC carrier for digital front-end applications in the CERN BE-BI group
Summary
The GEFE presents a small custom form factor (200 × 100 mm) conceived to operate inside a small “pizza box" in the front-end, close to the beamlines. The GBTx communicates with an FPGA-based back-end board (e.g. VFC-HD), configured with the GBT-FPGA core [8] This communication is done through a high-speed optical link (the Versatile Link), using a radiation tolerant optical transceiver named VTRx [9], the other main component of the GBT/Versatile Link. Besides the GBT/Versatile Link, the GEFE board features the ESLT, enabling serial data transmission/reception at low-speed over copper cable through long distances (tested up to 2 km at 10 Mbps) This fully custom electrical link based on discrete components was developed at CERN by the BE-BI-QP section, with the purpose of communicating the back-end with the front-end cards in the BPM system of the CERN Neutrinos to Gran Sasso (CNGS) project [12]. In GEFE, the high-speed lines (DP) of the FMC HPC connector do not comply with the ANSI/VITA 57.1, since they are used as user-specific I/Os and can be used for special functions (e.g. SC e-link to FMC HPC, ProAsic FPGA programming from JTAG master on FMC, etc.)
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