Abstract
Initiated in 2009 to emulate the GBTX (Gigabit Transceiver) serial link and test the first GBTX prototypes, the GBT-FPGA project is now a full library, targeting FPGAs (Field Programmable Gate Array) from Altera and Xilinx, allowing the implementation of one or several GBT links of two different types: “Standard” or “Latency-Optimized”. The first major version of this IP Core was released in April 2014. This paper presents the various flavours of the GBT-FPGA kit and focuses on the challenge of providing a fixed and deterministic latency system both for clock and data recovery for all FPGA families.
Highlights
1.2 The GBT-FPGA core In order to facilitate the in-system implementation and the user support of the GBT-FPGA, the different components of the core are integrated in a single module called “GBT Bank”
Each GBT Link is composed of a GBT Transmitter (TX), a GBT Receiver (RX) and a MultiGigabit Transceiver (MGT)
A fully automated testbench was used to verify the determinism in clock phase and data latency as well as to measure the drift of the clocks phase versus temperature, making sure that the previously mentioned drift does not affect the reliability of the system
Summary
The unification of TTC, EC and DAQ functionality on the new link simplifies the topology and reduces the number of optical links This topology introduces new technical challenges related to the reference clock that will have to be recovered from the incoming data stream [10]. Trigger related electronic systems in High Energy Physics (HEP) experiments, such as TTC links, require a fixed, low and deterministic latency in the transmission of the clock and data to ensure correct event building. The GBT-FPGA project provides two types of implementation for the transmitter and the receiver: the “Standard” version, targeted for non-time critical applications and the “LatencyOptimized” version, ensuring a fixed, low and deterministic latency of the clock and data (at the cost of a more complex implementation). The results of the characterization of the GBT-FPGA core in terms of latency versus temperature are presented
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
