The fundamental downscaling limit of field effect transistors

Denis Mamaluy,Xujiao Gao

doi:10.1063/1.4919871

Abstract

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.

Highlights

We predict that within 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached
ITRS projects5 that the emerging trend of Si MultiGate FET (MuGFET) technology should allow Moore’s law to continue for at least another decade until 6-nm gate length is reached
We have initiated this study by utilizing the recent ITRS projections5 for CMOS technology downscaling and characteristics to compute the device switching energy, Es 1⁄4 CgVg2, where Cg is the gate capacitance and Vg is the gate voltage needed to turn on a FET device

Summary

Introduction

We predict that within 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. We have initiated this study by utilizing the recent ITRS projections5 for CMOS technology downscaling and characteristics to compute the device switching energy, Es 1⁄4 CgVg2, where Cg is the gate capacitance and Vg is the gate voltage needed to turn on a FET device.

Results

Conclusion