The FPGA time-to-digital converter for the large-scale detector TREK based on multi-wire drift chambers

Abstract

The new large-scale coordinate-tracking detector TREK is under construction in MEPhI. It is based on 264 multi-wire drift chambers (4000× 508× 112 mm3 size) developed in IHEP for experiments on the neutrino channel of the U-70 accelerator, and will have 250 m2 of continuous effective area. The main goal of the project is the solution of so-called “muon puzzle”: the unpredicted by any theory excess of high multiplicity muon bundles generated by ultra-high energy primary cosmic rays. Besides of a set of field-forming wires, each multi-wire drift chamber has 4 signal ones. The current from these wires is processed by the shaper-amplifier AMP-4, mounted on the front of the chamber. It generates LVDS pulses that should be processed by multi-channel TDC that faces two main requirements: large matching window (more than 6000 ns) with last significant digit (LSD) less than 10 ns and capability to hold more than 50 hits per channel in a single event. These conditions were fulfilled by the new time-to-digital converter developed on the basis of Cyclone V FPGA in MEPhI. This paper presents the design of the TDC, its main features and the first benchmarks of its performance.