Abstract
A design of single precision floating point adder based on FPGA is presented,by analysing the form of real number formed on IEEE 754 and the storage format of IEEE 754 single-precision floating point,the addition arithmetic process which is easy to realized by using FPGA is put forward,the split of module based on the arithmetic process facilitates the realization of pipeline designing,so the single precision floating point adder introduce by this paper has powerful operation process ability.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
