Abstract
A planarized Ti-polycide gate structure with high thermal stability has been developed using a chemical-mechanical polishing (CMP) process for the application of high-speed DRAM devices. For a given gate length and without any thermal annealing, the planarized Ti-polycide structure developed via a novel gate line formation technology manifested a substantially lower gate line resistance than that produced by a conventional processing method. In addition, the agglomeration of the TiSi/sub 2/ gate in a deep submicron regime was suppressed even after high-temperature cycling at 850/spl deg/C for 300 min, owing to a negligible local stress at the corner of the active and field region.
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