Abstract

The demand for integrated telecommunication network infrastructure has increased, and 100 Gbps optical transceivers are a critical part of this infrastructure. In this paper, an efficient firmware design scheme is proposed for a 100 Gbps C form-factor pluggable (CFP) optical transceiver based on the multi-source agreement standard for optical transceivers. In the proposed method, a field programmable gate array (FPGA) approach is used to integrate the CFP communication interface and register structure, and a micro controller unit (MCU) is employed to implement the operation of the CFP optical transceiver. This paper also proposed monitoring techniques using high-order polynomials for accurate optical power monitoring of CFP optical transceivers. To ensure that the implemented firmware satisfies the proposed design scheme, an actual testbed was constructed and the performance of the firmware was evaluated. The results demonstrate that the proposed design scheme not only satisfies standard items but also achieved an average monitoring accuracy of more than 90%. In addition, the proposed scheme can be applied to 200/400G CFP optical transceivers in the future. By implementing the CFP firmware using the proposed method, manufacturers can ensure quality while reducing cost and development time.

Highlights

  • In recent years, the demand for integrated telecommunication networks has increased because of the rapid increase in traffic due to the expansion of information technology devices such as smart devices and intelligent Internet-of-Things devices

  • The design architecture proposed in this paper consists of external analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), and the micro controller unit (MCU) controls them through a communication interface to ensure channel scalability and firmware stability

  • C form-factor pluggable (CFP) operation, alarm operation according to the received optical power, data throughput for transmission/reception, and digital diagnostic monitoring (DDM) accuracy are presented

Read more

Summary

Introduction

The demand for integrated telecommunication networks has increased because of the rapid increase in traffic due to the expansion of information technology devices such as smart devices and intelligent Internet-of-Things devices. CFP firmware is responsible for monitoring and controlling the state of the CFP transceiver by configuring the memory and updating the information according to the standard. Intergrated circuit (IC) manufacturer has introduced an IC with a basic interface for designing CFP firmware, but it only provides CFP transceiver and host interface functions, rather than a design method for the entire operation of the optical transceiver [15]. We propose a CFP firmware design method based on the MSA standard. By implementing the CFP firmware using the proposed design method, quality can be ensured and cost and development time can be reduced. We proposed a memory access method to ensure stable memory access for optical transceiver control and monitoring.

Related Work
CFP Transceiver Management Interface
CFP Register
CFP Transceiver Control and DDM
Overall Structure Design
FPGA Design
MCU Design
NVM Function
DDM Function
CFP Status Management Function
IC Communication Interface Function
Optical Transceiver Testbed
Temperature Testbed
Functional Test Result
Performance Test Result
Conclusions
Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call