The Fault Tolerant CMOS Logical C-Element for Digital Devices Resistant to Single Nuclear Particles

Abstract

The TCAD simulation results of the new CMOS logical C-element based on the trigger with reduced switching delay and two tristate inverters designed using 65-nm bulk CMOS technology are presented. Transistors of the element are divided into two groups so that charge collection from the track of a single nuclear particle by transistors of one group only cannot cause the C-element trigger to fail. Charge collection from tracks with linear energy transfer of 60 MeV.cm2/mg does not lead to changes of the logical function of the element and to failures when the C-element transmits common-mode logic signals. The nature of charge collection from tracks does not significantly depend on operation mode of the C-element as well as on the moment of setting the common-mode signals for state switching or antiphase signals for state storage.