Abstract
The Exemplar X-Class is the second generation SPP from HP/Convex. It is a ccNUMA (cache coherent nonuniform memory access) architecture comprised of multiple nodes. We describe the evolution from the first generation systems to the current S- and X-class systems. Each node may contain up to 16 PA-8000 processors, 16 Gbytes of memory and 8 PCI busses. The peak performance of each node is 11.5 Gflops. Memory access is UMA within each node and is accomplished via a nonblocking crossbar. Each node can be correctly considered as a symmetric multiprocessor. The interconnect between nodes is a derivative of the IEEE standard, SCI, which permits up to 32 nodes to be connected in a 2 dimensional topology. The system includes features to aid high performance engineering/scientific computations. Among these are a hardware bcopy engine, interconnect caches, and memory and cache based semaphores.
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