The epitaxial deposition of silicon on insulating substrates for MOS circuitry

Abstract

Parasitic capacitances associated with large junction areas in bulk silicon MOS transistors can be virtually eliminated if MOS devices can be fabricated in silicon films on insulating substrates. The problem has been not only one of achieving suitable electrical properties in the thin films, but also of maintaining the “as-deposited” properties during the thermal treatments used in device processing. The changes in the electrical properties have made it particularly difficult to reproducibly fabricate deep depletion MOS devices, which require the deposition of thin films (less than 1.5μ) with carrier concentrations as low as ∼5 × 1014 per cu cm. Modifications in the film deposition procedures and in the pregrowth treatment of the substrate have enhanced the thermal stability of the electrical properties sufficiently for the fabrication of deep depletion MOS devices on 1.0 μ thick films. Procedures have also been developed for the deposition of bothn-andp-type silicon on the same insulating substrate by a “two-stage” epitaxial process. Thus, both components of the complementary pair circuit may be enhancement mode devices. Since relatively high carrier concentrations can be employed in the discreten andp-type films, the doping requirements and the processing of the device structures have been considerably eased. The deposition conditions and the ability to deposit high quality silicon on a substrate surface from which silicon has been previously removed are interrelated and are important considerations in performing the two-stage epitaxial process.